1. Field of the Invention
The present invention relates to a control device for controlling a buffer memory that can store n data words and is capable of being used for data transfer between a first system and a second system, with the control device including a write pointer and a read pointer.
2. Description of Related Art
The present invention is especially valuable in the case of two electronic systems exchanging data asynchronously or mesochronously. The data exchanged between two systems is said to be “asynchronous” if the two systems operate with clocks of different frequencies. A data exchange is said to be “mesochronous” if the two systems operate with clocks that have the same frequency but are phase-shifted relative to each other.
Many electronic circuits, integrated or otherwise, have independent systems that operate at the rhythm of clock signals that have different frequencies and/or that are phase-shifted relative to each other. This is the case, for example, when a processor handles the data at a high frequency and then transmits it to downstream circuits operating at a lower frequency. This is also the case when two systems have their paces set by the same clock signal generator, but with the first system being at a greater distance from the clock signal generator (in terms of length of the wire conveying the clock signal) than the second system, so that the clock signal received by the first system is phase-shifted relative to the clock signal received by the second system.
The transfer of data between two systems can be done, for example, using a buffer memory.
FIG. 1 shows a circular buffer memory comprising one write-accessible port and one read-accessible port. The memory has n storage registers R1 to Rn, one input selection circuit, one output selection circuit, and one control device. The n storage registers store data words in transit between the first system and the second system. The input selection circuit comprises a data input connected to a data output of the first system for receiving data to be transmitted, and n outputs each connected to one input of one of the n storage registers R1 to Rn. The input selection circuit also has a control input to receive a signal indicating the output to which the data input is to be connected. The output selection circuit comprises n data inputs each connected to one data output of the n registers R1 to Rn, one data output connected to one data input of the second system, and one control input. When the first system commands a write operation (WRITE signal) and/or when the second system commands a read operation (READ signal), the control device produces control signals WRITE_SELECT and/or READ_SELECT for writing a piece of data to a register and/or reading a piece of data from a register, so that the pieces of data are read from the memory in the order in which they were written.
The control device comprises a write pointer and a read pointer. In practice, these pointers are shift registers whose contents indicate the storage registers, from among the storage registers R1 to Rn, in which a next word is to be written and a next word is to be read, respectively. The contents of the write pointer and the read pointer, respectively, are updated at each write operation and each read operation, respectively, in a register of the memory.
When the first system and the second system which use the buffer memory communicate asynchronously or mesochronously, phenomena of instability (commonly called “metastability”) may appear; the second system receives a piece of data different from that transmitted by the first system when a data signal or command signal inside the memory or associated control device changes its state upon a command from the first system and does not have the time necessary to stabilize its value before being exploited by the second system.
To prevent instability in the case of a transfer of data through a unique storage register whose rate is set by the clock of the first system (i.e., the system which stores data in the storage register), one elementary technique is the addition, at output of the storage register, of a synchronization circuit. This synchronization circuit is, for example, a two-bit shift register whose rate is set according to the clock of the second system (i.e., the system that receives the data contained in the storage register).
This technique introduces a latency of one to two clock cycles. Latency is the time between the instant when a signal changes its state and the instant when its value is stable and guaranteed. In the case of the addition of a synchronization circuit, the latency of the control device is equal to the transit time in the synchronization circuit.
Other techniques are also used to prevent instabilities in buffer memories (such as FIFO memories), banks of registers, or dual-port memories which are more complex than a simple register.
A first technique described in French Patent No. 2 849 228 or U.S. Patent Application No. 2004/0230723 uses a dual-flag mechanism (or “acknowledgment-due mechanism”) to ensure accurate reception of the data by the second system, and ghost registers (images of a pointer) to acquire a modification of the content of a pointer before it is exploited. Although the problem of the metastability of the data is well resolved, one drawback of this technique is high latency, of about 2 to 6 clock cycles. This is the time needed for the acknowledgment of reception sent by the second system to be received by the first system after the updating and exploitation of the content of the ghost registers.
A second technique described in U.S. Pat. No. 5,598,113 uses a control device comprising, as a complement, read and write pointers, one n-bit state register (register 1150) updated according to the content of the write pointer and the read pointer (see, e.g., FIGS. 11 and 12 and their associated description). Each bit of the state register indicates whether the same-ranking register of the buffer memory contains a data word (that can be read by the second system) or if the register is empty (so that it can be written to by the first system).
The control device also has a write management circuit in which the signals output from the state register (register 1150) are used to determine whether the memory is full (circuit 1050 of D3) and the result (signal 1151) is synchronized (circuit 1135) before it is used (signal 1115) to update the write pointer (1130). Also, the control device comprises a read management circuit in which the signals output from the state register are synchronized (circuit 1160 of D3) with the clock signal of the second system before being used to determine whether the memory is empty (circuit 1165), with the result (the signal 1175) being then used for the updating of the read pointer (1170).
One drawback of this technique is that it necessitates the use of a state register to manage the content of the memory. This increases the silicon surface area of the control device. Furthermore, this state register is obtained by jam-type latch circuits. Such latch circuits are more robust than D-type latch circuits or flip-flop circuits with respect to the metastability phenomena that appear in systems communicating mesochronously.